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10-bit, 210 msps adc ad9410 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2000C2007 analog devices, inc. all rights reserved. features snr = 54 db with 99 mhz analog input 500 mhz analog bandwidth on-chip reference and track and hold 1.5 v p-p differential analog input range 5.0 v and 3.3 v supply operation 3.3 v cmos/ttl outputs power: 2.1 w typical at 210 msps demultiplexed outputs each at 105 msps output data format option data sync input and data clock output provided interleaved or parallel data output option applications communications and radars local multipoint distribution services (lmds) high-end imaging systems and projectors cable reverse paths point-to-point radio links functional block diagram t/h ds clk? ds clk+ dfs i/p reference dgnd agnd dco 10 dco ad9410 10 10 adc 10-bit core timing and synchronization port b port a ref in ref out v d v dd v cc or a d a9 ?d a0 or b d b9 ?d b0 a in a in 01679-001 figure 1. general description the ad9410 is a 10-bit monolithic sampling analog-to-digital converter (adc) with an on-chip track-and-hold circuit and is optimized for high speed conversion and ease of use. the product operates at a 210 msps conversion rate, with outstanding dynamic performance over its full operating range. the adc requires a 5.0 v and 3.3 v power supply and up to a 210 mhz differential clock input for full performance operation. no external reference or driver components are required for many applications. the digital outputs are ttl-/cmos-compatible and separate output power supply pins also support interfacing with 3.3 v logic. the clock input is differential and ttl-/cmos-compatible. the 10-bit digital outputs can be operated from 3.3 v (2.5 v to 3.6 v) supplies. two output buses support demultiplexed data up to 105 msps rates and binary or twos complement output coding format is available. a data sync function is provided for timing-dependent applications. an output clock simplifies interfacing to external logic. the output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching output data. fabricated on an advanced bicmos process, the ad9410 is available in an 80-lead thin quad flat package, exposed pad specified over the industrial temperature range (?40c to +85c). product highlights 1. high resolution at high speedthe architecture is spe- cifically designed to support conversion up to 210 msps with outstanding dynamic performance. 2. demultiplexed outputoutput data is decimated by two and provided on two data ports for ease of data transport. 3. output data clockthe ad9410 provides an output data clock synchronous with the output data, simplifying the timing between data and other logic. 4. data synchronizationa ds input is provided to allow for synchronization of two or more ad9410s in a system, or to synchronize data to a specific output port in a single ad9410 system.
ad9410 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 switching specifications .............................................................. 4 digital specifications ................................................................... 4 ac specifications .......................................................................... 5 absolute maximum ratings ............................................................ 7 explaination of test levels .......................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ..............................8 ter mi nolo g y .................................................................................... 10 equivalent circuits ..................................................................... 12 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 16 using the ad9410 ...................................................................... 16 analog input ............................................................................... 16 digital outputs ........................................................................... 16 clock outputs (dco, dco ) .................................................... 16 volt age reference ....................................................................... 17 timing ......................................................................................... 17 data sync (ds) ........................................................................... 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 7/07rev. 0 to rev. a updated format..................................................................universal deleted 80-lead lqfp_ep ...............................................universal added 80-lead tqfp_ep.................................................universal changes to figure 1 and general description ............................. 1 changes to table 2 and table 3....................................................... 4 changes to figure 2.......................................................................... 6 changes to note 1............................................................................. 7 changes to figure 3 and table 6..................................................... 8 changes to terminology section.................................................. 10 changes to figure 6........................................................................ 12 deleted evaluation board section................................................ 14 renamed encode input section, clock input section and changes to clock input section, clock outputs (dco, dco ) section, figure 26, and figure 27 ................................................. 16 changes to data sync (ds) section ............................................. 17 changes to figure 29...................................................................... 18 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 19 10/00revision 0: initial version
ad9410 rev. a | page 3 of 20 specifications dc specifications v dd = 3.3 v, v d = 3.3 v, v cc = 5.0 v; 2.5 v external reference; a in = ?0.5 dbfs; clock input = 210 msps; t a = 25c; unless otherwise noted. table 1. parameter temp test level min typ max unit resolution 10 bits dc accuracy no missing codes full iv guaranteed differential nonlinearity 25c i ?1.0 0.5 +1.25 lsb full vi ?1.0 +1.5 lsb integral nonlinearity 25c i ?2.5 1.65 +2.5 lsb full vi ?3.0 +3.0 lsb gain error 25c i ?6.0 0 +6.0 % fs gain temperature coefficient full v 130 ppm/c analog input input voltage range (with respect to a in ) full v 768 mv p-p common-mode voltage full v 3.0 v input offset voltage 25c i ?15 +3 +15 mv full vi ?20 +20 mv reference voltage full vi 2.4 2.5 2.6 v reference temperature coefficient full v 50 ppm/c input resistance full vi 610 875 1250 input capacitance 25c v 3 pf analog bandwidth, full power 25c v 500 mhz power supply power dissipation ac 1 25c v 2.1 w power dissipation dc 2 full vi 2.0 2.4 w i vcc 2 full vi 128 145 ma i vd 2 full vi 401 480 ma power supply rejection ratio, psrr 25c i ?7.5 +0.5 +7.5 mv/v 1 clock input = 210 msps, a in = C0.5 dbfs, 10 mhz sine wave, i vdd = 31 ma typical at c load = 5 pf. 2 clock input = 210 msps, a in = dc, outputs not switching.
ad9410 rev. a | page 4 of 20 switching specifications v dd = 3.3 v, v d = 3.3 v, v cc = 5.0 v; 2.5 v external reference; a in = ?0.5 dbfs; clock input = 210 msps; t a = 25c; unless otherwise noted. table 2. parameter temp test level min typ max unit switching performance maximum conversion rate full vi 210 msps minimum conversion rate full iv 100 msps clock pulse width high, t eh 25c iv 1.2 2.4 ns clock pulse width low, t el 25c iv 1.2 2.4 ns aperture delay, t a 25c v 1.0 ns aperture uncertainty (jitter) 25c v 0.65 ps rms output valid time, t v full vi 3.0 ns output propagation delay, t pd full vi 7.4 ns output rise time, t r 25c v 1.8 ns output fall time, t f 25c v 1.4 ns clkout propagation delay, t cpd 1 full vi 2.6 4.8 6.4 ns data to dco skew, (t pd C t cpd ) full iv 0 1 2 ns ds setup time, t sds full iv 0.5 ns ds hold time, t hds full iv 0 ns interleaved mode (a, b latency) full vi a = 6, b = 6 cycles parallel mode (a, b latency) full vi a = 7, b = 6 cycles 1 c load = 5 pf. digital specifications v dd = 3.3 v, v d = 3.3 v, v cc = 5.0 v; 2.5 v external reference; a in = ?0.5 dbfs; clock input = 210 msps; t a = 25c; unless otherwise noted. table 3. parameter temp test level min typ max unit digital inputs dfs, input logic 1 voltage full iv 4 v dfs, input logic 0 voltage full iv 1 v dfs, input logic 1 current full v 50 a dfs, input logic 0 current full v 50 a i/p input logic 1 current 1 full v 400 a i/p input logic 0 current 1 full v 1 a clk+, clk? differential input voltage full iv 0.4 v clk+, clk? differential input resistance full v 1.6 k clk+, clk? common-mode input voltage 2 full v 1.5 v ds, ds differential input voltage full iv 0.4 v ds, ds common-mode input voltage full v 1.5 v digital input pin capacitance 25c v 3 pf digital outputs logic 1 voltage (v dd = 3.3 v) full vi v dd C 0.05 v logic 0 voltage (v dd = 3.3 v) full vi 0.05 v output coding binary or twos complement 1 i/p pin logic 1 = 5 v, logic 0 = gnd. it is recommended to use a series 2.5 k (10%) resistor to v dd when setting to logic 1 to limit input current. 2 see clock input section.
ad9410 rev. a | page 5 of 20 ac specifications v dd = 3.3 v, v d = 3.3 v, v cc = 5.0 v; 2.5 v external reference; a in = ?0.5 dbfs; clock input = 210 msps; t a = 25c; unless otherwise noted. table 4. parameter temp test level min typ max unit dynamic performance transient response 25c v 2 ns overvoltage recovery time 25c v 2 ns signal-to-noise ratio, snr (without harmonics) f in = 10.3 mhz 25c i 52.5 55 db f in = 82 mhz 25c i 52 54 db f in = 160 mhz 25c v 53 db signal-to-noise ratio, sinad (with harmonics) f in = 10.3 mhz 25c i 51 54 db f in = 82 mhz 25c i 50 53 db f in = 160 mhz 25c v 52 db effective number of bits, enob f in = 10.3 mhz 25c i 8.3 8.8 bits f in = 82 mhz 25c i 8.1 8.6 bits f in = 160 mhz 25c v 8.4 bits second harmonic distortion f in = 10.3 mhz 25c i ?56 ?65 dbc f in = 82 mhz 25c i ?55 ?63 dbc f in = 160 mhz 25c v ?65 dbc third harmonic distortion f in = 10.3 mhz 25c i ?58 ?69 dbc f in = 82 mhz 25c i ?57 ?67 dbc f in = 160 mhz 25c v ?62 dbc spurious-free dynamic range, sfdr f in = 10.3 mhz 25c i 56 61 dbc f in = 82 mhz 25c i 54 60 dbc f in = 160 mhz 25c v 58 dbc two-tone intermod distortion, imd 1 f in1 = 80.3 mhz, f in2 = 81.3 mhz 25c v 58 dbfs 1 in1, in2 level = ?7 dbfs.
ad9410 rev. a | page 6 of 20 t eh t el 1/ f s t a t sds t cpd sample n?2 sample n?1 sample n sample n+1 sample n+2 sample n+3 sample n+4 sample n+5 sample n+6 t v t pd t hds static static static static static invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid data n+1 data n+3 data n data n+2 data n+1 data n data n+2 interleaved data out parallel data out a in clk+ ds port a d7 to d0 port b d7 to d0 dco port a d7 to d0 port b d7 to d0 clk? ds dco 01679-002 figure 2. timing diagram
ad9410 rev. a | page 7 of 20 absolute maximum ratings table 5. parameter rating v d , v cc , v dd 6 v analog inputs 0 v to v cc + 0.5 v digital inputs 0 v to v dd + 0.5 v vref in 0 v to v d + 0.5 v digital output current 20 ma operating temperature range ?55c to +125c storage temperature range ?65c to +150c maximum junction temperature 1 150c 1 adequate dissipation of power from the ad9410 relies on all power and ground pins of the device being soldered directly to a copper plane on a pcb. in addition, the thermally enhanced package of the ad9410bsvz has an exposed paddle on the bottom that must be soldered to a large copper plane, which, for convenience, can be the ground plane. sockets for package style of the ad9410 device are not recommended. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explaination of test levels test level i. 100% production tested. ii. 100% production tested at 25c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25c; guaranteed by design and characterization testing for industrial temperature range. esd caution
ad9410 rev. a | page 8 of 20 pin configuration and fu nction descriptions 01679-003 pin 1 identifier 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 616263 64 65 66 676869 70 7172 737475 76 77 787980 ad9410 top view 80-lead thin quad flat package (not to scale) agnd agnd v cc ref out ref in dnc v cc agnd agnd a in agnd agnd v cc v cc agnd agnd clk+ agnd v dd dgnd d a4 d a3 d a2 d a1 d a0 (lsb) v dd dgnd dco dco dgnd v dd or b d b9 (msb) d b8 d b7 d b6 d b5 v dd i/p dfs agnd agnd v d v d agnd agnd agnd agnd v d v d dgnd v dd or a d a9 (msb) d a8 d a7 d a6 d a5 agnd ds agnd v d v d agnd agnd agnd agnd v d v d dgnd v dd (lsb) d b0 d b1 d b2 d b3 d b4 dgnd a in clk? ds dnc = do not connect. figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic function 1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24, 27, 28, 29, 30, 71, 72, 73, 74, 77, 78 agnd analog ground. 3, 7, 14, 15 v cc 5 v supply. (regulate to within 5%.) 4 ref out internal reference output. 5 ref in internal reference input. 6 dnc do not connect. 10 a in analog inputtrue. 11 a in analog inputcomplement. 18 clk+ clock inputtrue. 19 clk? clock inputcomplement. 22 ds data sync (input)true. tie low if not used. 23 ds data sync (input)complement. float and deco uple with 0.1 f capacitor if not used. 25, 26, 31, 32, 69, 70, 75, 76 v d 3.3 v analog supply. (regulate to within 5%.) 33, 40, 49, 52, 59, 68 dgnd digital ground. 34, 41, 48, 53, 60, 67 v dd 3.3 v digital output supply. (2.5 v to 3.6 v) 35 to 39 d b0 to d b4 digital data output for channel b. (lsb = d b0 .) 42 to 46 d b5 to d b9 digital data output for channel b. (msb = d b9 .) 47 or b data overrange for channel b. 50 dco clock outputcomplement.
ad9410 rev. a | page 9 of 20 pin no. mnemonic function 51 dco clock outputtrue. 54 to 58 d a0 to d a4 digital data output for channel a (lsb = d a0 ). 61 to 65 d a5 to d a9 digital data output for channel a (msb = d a9 ). 66 or a data overrange for channel a. 79 dfs data format select. high = twos complement, and low = binary. 80 i/p interleaved or parallel output mode. low = pa rallel mode, and high = interleaved mode. if tying high, use a current limiting series resistor (2.5 k) to the 5 v supply.
ad9410 rev. a | page 10 of 20 terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the clock command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 and taking the peak measurement again. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) enob is calculated from the measured sinad based on the equation 02.6 log2076.1 ? ? ? ? ? ? ? ? +? = amplitude input amplitude scalefull db sinad enob measured clock pulse width/duty cycle pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve rated performance; pulse width low is the minimum time the clock pulse should be left in low state. at a given clock rate, these specifications define an acceptable clock duty cycle. full-scale input power expressed in dbm. computed using the equation ? ? ? ? ? ? ? ? ? ? ? ? = 001.0 log10 2 input fullscale fullscale z v power rms harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least-square curve fit. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of clk+ and clk? and the time when all output data bits are within valid logic levels. out-of-range recovery time out-of-range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. noise (for any range within the adc) ? ? ? ? ? ? ? = 10 10001.0|| dbfs dbm noise signal fs z v where: z is the input impedance. fs is the full scale of the device for the frequency in question. signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quantization noise. power supply rejection ratio (psrr) the ratio of a change in input offset voltage to a change in power supply voltage.
ad9410 rev. a | page 11 of 20 signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 0.5 db below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 0.5 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. it may be reported in dbc (that is, degrades as signal level is lowered) or dbfs (always related back to converter full scale). transient resp onse time transient response time is defined as the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (that is, degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc. table 7. output coding (vref = 2.5 v) step a in ? a in digital outputs offset binary digital outputs twos complement or a , or b >+0.768 11 1111 1111 01 1111 1111 1 1023 +0.768 11 1111 1111 01 1111 1111 0 513 +0.0015 10 0000 0001 00 0000 0001 0 512 0.0 10 0000 0000 00 0000 0000 0 511 C0.0015 01 1111 1111 11 1111 1111 0 0 C0.768 00 0000 0000 10 0000 0000 0 < C0.768 00 0000 0000 10 0000 0000 1
ad9410 rev. a | page 12 of 20 equivalent circuits 1.5k ? 2.25k ? 1.5k ? 2.25k ? v cc a in a in 01679-004 figure 4. equivalent analog input circuit v ref in v cc 0 1679-005 figure 5. equivalent reference input circuit 17k ? 17k? 8k ? 8k ? clk+ 100 ? 100 ? clk? 450 ? 450 ? v cc 0 1679-006 figure 6. equivalent clock input circuit v dd 01679-007 digital output figure 7. equivalent digital output circuit vref out v cc 01679-008 figure 8. equivalent reference output circuit 100k ? dfs v cc 01679-009 figure 9. equivalent dfs input circuit 7.5k ? ds 300? 17.5k ? 300 ? ds v cc 01679-010 figure 10. equivalent ds input circuit 7.5k ? i/p 300 ? 17.5k ? v cc 01679-011 figure 11. equivalent i/p input circuit
ad9410 rev. a | page 13 of 20 typical performance characteristics frequency (mhz) 0 0 amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 105 encode = 210msps a in = 40mhz @ ?0.5dbfs snr = 54.5db sinad = 53.5db 01679-012 figure 12. single tone at 40 mhz; 210 msps frequency (mhz) 0 0 amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 105 encode = 210msps a in = 100mhz @ ?0.5dbfs snr = 53.5db sinad = 52.5db 01679-013 figure 13. single tone at 100 mhz; 210 msps frequency (mhz) 0 0 amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 105 encode = 210msps a in = 160mhz @ ?0.5dbfs snr = 53db sinad = 52db 01679-014 figure 14. single tone at 160 mhz; 210 msps 51 snr/sinad (db) 50 49 48 47 46 45 53 55 snr sinad 52 54 01679-015 a in (mhz) 0 50 100 150 200 250 figure 15. snr/sinad vs. a in ; 210 msps sample rate (msps) 53.0 snr/sinad (db) 52.5 52.0 51.5 51.0 50.5 50.0 54.0 55.0 snr sinad 53.5 54.5 01679-016 100 120 140 160 180 200 220 240 figure 16. snr/sinad vs. sample rate; a in = 70 mhz pulse width (ns) 40 snr/sinad (db) 35 30 55 60 50 45 sinad snr 01679-017 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 figure 17. snr/sinad vs. cl ock positive pulse width (f s = 210 msps, a in = 70 mhz)
ad9410 rev. a | page 14 of 20 frequency (mhz) 0 0 amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 105 encode = 210msps a in 1, a in 2 = ?7dbfs sfdr = 62dbfs 01679-018 figure 18. two tone test a in 1 = 80.3 mhz, a in 2 = 81.3 mhz 54.5 snr/sinad (db) 54.0 53.5 53.0 52.5 52.0 51.5 55.0 55.5 snr sinad 01679-019 temperature (c) ?40 ?20 0 20 40 60 80 100 120 figure 19. snr/sinad vs. temperature, 210 msps, a in = 70 mhz temperature (c) 70 second and third harmonic amplitude (db) 68 66 64 62 60 58 72 74 h2 h3 ?40 ?20 0 20 40 60 80 100 120 01679-020 figure 20. second and third harmonics vs. temperature; a in = 70 mhz, 210 msps analog supply (v) 2.48 vref (v) 2.47 2.46 2.51 2.52 2.50 2.49 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 01679-021 figure 21. vref out vs. analog 5 v supply sample rate (msps) 110 100 supply current (ma) 60 10 260 310 210 160 220 360 410 460 iahi3 iahi5 ivdd 120 140 160 180 200 01679-022 figure 22. power supply currents vs. sample rate load current (ma) 2.35 0 vref (v) 2.30 2.25 1.5 2.40 2.5 2.45 2.50 2.55 01679-023 0.5 1.0 2.0 figure 23. vref out vs. i load
ad9410 rev. a | page 15 of 20 temperature (c) vref (v) 2.503 2.502 2.501 2.500 2.499 2.498 2.497 2.496 80 60 40 20 0 ?20 ?40 01679-024 figure 24. vref out vs. temperature timing specifications (ns) 5.1 4.9 4.7 4.5 4.3 4.1 3.9 temperature (c) 80 60 40 20 0 ?20 ?40 01679-025 t pd t v t cpd figure 25. t pd , t v , t cpd vs. temperature
ad9410 rev. a | page 16 of 20 theory of operation the ad9410 architecture is optimized for high speed and ease of use. the analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the flash 10-bit core. for ease of use, the part includes an on-board reference and input logic that accepts ttl, cmos, or pecl levels. using the ad9410 clock input any high speed adc is extremely sensitive to the quality of the sampling clock provided by the user. a track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock combines with the desired signal at the adc output. for that reason, considerable care has been taken in the design of the clock input of the ad9410, and the user is advised to give commensurate thought to the clock source. to limit snr degradation to less than 1 db, a clock source with less than 1.25 ps rms jitter is required for sampling at nyquist (for example, the valpey fisher vf561). note that required jitter accuracy is a function of input frequency and amplitude. refer to the analog devices, inc. an-501 application note, aperture uncertainty and adc system performance , for more information. the clock input is fully ttl/cmos compatible. the clock input can be driven differentially or with a single-ended signal. best performance is obtained when driving the clock differentially. both clock inputs are self-biased to 1/3 v cc by a high impedance resistor divider (see the equivalent circuits section). single- ended clocking, which can be appropriate for lower frequency or nondemanding applications, is accomplished by driving the clock input directly and placing a 0.1 f capacitor at clock. clk+ clk? ad9410 ttl/ cmos gate 0.1f 01679-026 figure 26. driving single-ended clock input at ttl/cmos levels an example where the clock is obtained from a pecl driver is shown in figure 27 . note that the pecl driver is ac-coupled to the clock inputs to minimize input current loading. the ad9410 can be dc-coupled to pecl logic levels, resulting in the clock input currents increasing to approximately 8 ma typical, which is due to the difference in dc bias between the clock inputs and a pecl driver (see the equivalent circuits section). clk+ clk? ad9410 pecl gate 0.1f 01679-027 0.1f gnd 510 ? 510 ? analog input the analog input to the ad9410 is a differential buffer. for best dynamic performance, impedances at a in and a in should match. the analog input has been optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades significantly if the analog input is driven with a single- ended signal. a wideband transformer, such as mini-circuits adt1-1wt, can be used to provide the differential analog inputs for applications that require a single-ended-to- differential conversion. both analog inputs are self-biased by an on-chip resistor divider to nominal 3 v (see the equivalent circuits section). special care was taken in the design of the analog input section of the ad9410 to prevent damage and corruption of data when the input is overdriven. the nominal input range is 1.5 v diff p-p. the nominal differential input range is 768 mv p-p 2. 2.616 input span (v) 3.384 3.000 a in a in 01679-028 figure 28. typical analog input levels digital outputs the digital outputs are ttl/cmos compatible for lower power consumption. the outputs are biased from a separate supply (v dd ), allowing easy interface to external logic. the outputs are cmos devices that swing from ground to v dd (with no dc load). it is recommended to minimize the capacitive load the adc drives by keeping the output traces short (<1 inch, for a total c load < 5 pf). it is also recommended to place low value (20 ) series damping resistors on the data lines to reduce switching transient effects on performance. clock outputs (dco, dco ) the input clock is divided by two and available off-chip at dco and dco . these clocks can facilitate latching off-chip, providing a low skew clocking solution (see figure 2 ). these clocks can also be used in multiple ad9410 systems to synchronize the adcs. depending on application, dco or dco can be buffered and used to drive the ds inputs on a second ad9410, ensuring synchronization. the on-chip clock buffers should not drive more than 5 pf to 7 pf of capacitance to limit switching transient effects on performance.
ad9410 rev. a | page 17 of 20 voltage reference a stable and accurate 2.5 v voltage reference is built into the ad9410 (vref out ). the input range can be adjusted by varying the reference voltage. no appreciable degradation in performance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage changes linearly within the 5% tolerance. timing the ad9410 provides latched data outputs, with six pipeline delays in interleaved mode (see figure 2 ). in parallel mode, the port a has one additional cycle of latency added on-chip to line up transitions at the data ports, resulting in a latency of seven cycles for the port a. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9410; these transients can detract from the dynamic performance of the converter. the minimum guaranteed conversion rate of the ad9410 is 100 msps. at internal clock rates below 100 msps, dynamic performance may degrade. note that lower effective sampling rates can be obtained simply by sampling just one output port decimating the output by two. lower sampling frequencies can also be accommodated by restricting the duty cycle of the clock such that the clock high pulse width is a maximum of 5 ns. data sync (ds) the data sync input, ds, can be used in applications requiring that a given sample appear at a specific output port a or port b. when ds is held high, the adc data outputs and clock do not switch and are held static. synchronization is accomplished by the assertion (falling edge) of ds, within the timing constraints t sds and t hds relative to an clock rising edge. (on initial synchronization, t hds is not relevant.) if ds falls within the required setup time (t sds ) before a given clock rising edge n, the analog value at that point is digitized and available at port b six cycles later (interleaved mode). the next sample, n+1, is sampled by the next rising clock edge and available at port a six cycles after that clock edge (interleaved mode). in dual parallel mode, port a has a seven cycle latency, and port b has a six cycle latency, but data is available at the same time.
ad9410 rev. a | page 18 of 20 daor da7 da8 da5 gnd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 gnd da6 da9 gnd 3.3va gnd 3.3va 3.3va gnd 3.3va gnd gnd e14 5v gnd e12 e16 5v e10 gnd vdd e11 e7 dbor gnd dcoc dcot gnd db9 db6 db7 da0 da1 da2 da3 da4 gnd vdd db8 vdd vdd gnd 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 dgnd dco dco dgnd dgnd gnd gnd vdd db5 gnd gnd db0 db1 db2 db4 gnd gnd 40 393837 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vdd 3.3va 3.3va gnd gnd 3.3va gnd 3.3va gnd gnd j9x j10x agnd ds ds agnd agnd agnd agnd agnd dgnd dgnd gnd 5v gnd gnd enct encc gnd gnd gnd e3 e6 5v gnd e1 1 t1 1:1 gnd j8 ain gnd 2 3 6 5 4 gnd gnd gnd gnd gnd 5v gnd ad9410 u3 gnd 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 c28 0.1 f 1 2 3 4 5 6 7 8 nc d d vbb vcc q q vee u1 5v gnd gnd j1 5v gnd gnd r15 330 ? gnd r11 330 ? enct encc gnd mc10el16 gnd gnd 5v p1 p5 p4 gnd vdd/3.3v gnd gnd 3.3va gnd 5v gnd vdac gnd ext ref gnd 1 2 3 4 1 2 3 4 1 2 3 4 gnd 5v 3.3va vdd ext ref vdac dgnd agnd agnd agnd agnd agnd agnd dfs i/p agnd agnd dnc agnd agnd agnd agnd agnd agnd clk+ clk? agnd db3 c1 10f c2 10f c3 10f c5 10f c4 10f r8 50? r18 24k ? r9 24k ? r19 8.2k ? r14 8.2k ? c6 0.1f c40 0.1f c7 0.1f c8 0.1f note: r3, r6, r7, r24 optional (can be zero ? ) c14 0.1f c11 0.1f c10 0.1f r6 100 ? r4 2.5k ? r7 100 ? r3 100 ? r24 100 ? c27 0.1f c26 0.1f ext ref c24 0.1f c25 0.1f c7 0.1f r23 50? r25x 50? c16 0.1f c15 0.1f r26 50 ? c19 0.1f c18 0.1f c22 0.1f c21 0.1f c12 0.1f 01679-029 v cc ref out ref in v cc r27 50? a in a in v cc v cc v d v d v d v d d b0 v dd d b1 d b2 d b3 d b4 v dd d b6 v dd d b5 d b7 d b8 d b9 or b v dd d a1 v dd d a0 d a2 d a3 d a4 d a5 d a6 d a7 d a8 d a9 or a v dd v d v d v d v d figure 29. pcb schematic example
ad9410 rev. a | page 19 of 20 outline dimensions compliant to jedec standards ms-026-aec-hd 091506-a 0.75 0.60 0.45 1.20 max 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 0.27 0.22 0.17 0.65 bsc lead pitch bottom view (pins up) 9.50 sq exposed pad 20 21 21 40 40 41 61 61 60 41 60 80 80 1 20 1 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 figure 30. 80-lead thin quad flat package, exposed pad [tqfp_ep] (sv-80-4) dimensions shown in millimeters ordering guide model temperature range package description option ad9410bsvz 1 ?40c to +85c 80-lead thin quad flat package, exposed pad [tqfp_ep] sv-80-4 1 z = rohs compliant part.
ad9410 rev. a | page 20 of 20 notes ?2000C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c01679-0-7/07(a)

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